ECC
The IP provides Single Error Correction - Double Error Detection (SECDED) capability. The ECC IP is available in Verilog HDL and optimized for the CME-M5 architecture.
Features
- • SECDED capability implemented using the Hamming Coding scheme
- • - Correct any single-bit errors, and detect any single-bit and double-bit error
- • Directly usable code for (72,64), (39,32), (36,29), (18,12) SECDED module provided
- • - (72,64): 8-bit ECC for 64-bit message
- • - (39,32): 7-bit ECC for 32-bit message
- • - (36,29): 7-bit ECC for 29-bit message
- • - (18,12): 6-bit ECC for 12-bit message
- • Separate encoder and decoder modules to support optimized integration with user logic
- • Optional input/output registered and pipeline implementation to provide increased maximum speed of operation
- • - Optional input/output registered implementation for encoder, which can have flexible 0, 1 or 2 clock
- • delay during writes for ECC computation
- • - Optional input/output registered and pipeline implementation for decoder, which can have flexible 0, 1,
- • 2 or 3 clock delay during reads
- • Use flag signals to reflect the status of received data in decoder
