SDR SDRAM Controller
This IP provides a simplified interface to industry standard SDR SDRAM. The SDR SDRAM Controller is available in Verilog HDL and optimized for the CME-M5 architecture.
Features
- • Supports interface with SDRAM at up to 133MHz, single data rate
- • Burst lengths of 1, 2, 4, 8 or full page burst
- • Supports user burst terminate. For burst length of 2, 4, 8 and full page, supports any burst length
- • that not exceed burst length, user can implement different burst length through control user_burst_end,
- • when user want to terminate the burst operation, active the usr_burst_end for 1 cycle
- • CAS latency of 2 or 3 clock cycles
- • Supports internal automatic refresh, the refresh period can be programmed
- • Supports external automatic refresh request, user can control the auto refresh process
- • Supports the NOP, READ, WRITE, AUTO_REFRESH, PRECHARGE, ACTIVATE, BURST_TERMINATE and
- • LOAD_MR commands
- • Supports for data-path widths of 4, 8, 16, 32, 64 and 72 bits
- • Supports user change mode register value through load mode register request, does not support change CAS latency through load mode register request
- • Supports user DQM control
